These devices are generally used for the active correction of the power factor (PFC) for power supply units with forced switching used in common electronic appliances such as computers, televisions, monitors, etc and to power fluorescent lamps, in other words pre-regulation stages with forced switching which have the task of absorbing from the network supply a current that is virtually sinusoidal and is in phase with network voltage. A power supply unit with forced switching of the present type therefore comprises a PFC and a DC-DC converter connected to the PFC output.
A traditional power supply unit with forced switching comprises a DC-DC converter and an input stage connected to the electric energy distribution network, consisting of a full-wave diode rectifier bridge and of a capacitor connected immediately downstream so as to produce a non-regulated direct voltage from the network alternating sinusoidal current. The capacitor has sufficiently large capacity because the ripples, i.e., undulation of the voltage across it is relatively small compared with the DC level. The bridge rectifier diodes therefore conduct only a small portion of each half cycle of the network voltage because the momentary value of the network voltage is lower than the voltage on the capacitor for most of the cycle. The current absorbed by the network will accordingly be a series of narrow pulses the amplitude of which is 5 to 10 times the resulting average value.
This has considerable consequences: the current absorbed from the line has peak and effective values that are much greater than in case of the absorption of sinusoidal current, the network voltage is distorted by the almost simultaneous pulsed absorption of all the appliances connected to the network, in the case of three-phase systems the current in the neutral conductor is greatly increased and the energy potential of the system for producing electric energy is poorly used. In fact, the wave shape of a pulsed current is very rich in odd harmonic distortions that, whilst not contributing to the power returned to the load, contribute to increasing the effective current absorbed by the network and therefore to increasing the dissipation of energy.
In quantitative terms this can be expressed in terms of power factor (PF), defined as the ratio between real power (the power that the power supply unit returns to the load plus the power dissipated inside it in the form of heat) and apparent power (the product of the effective network voltage for the effective absorbed current), both in terms of total harmonic distortion (THD), generally defined as the percentage ratio between energy associated with all the harmonic distortions of a superior order and that associated with the fundamental harmonic distortion. Typically, a power supply unit with a capacitive filter has a PF between 0.4-0.6 and a THD greater than 100%.
A PFC arranged between the rectifier bridge and the input of the DC-DC converter enables a virtually sinusoidal current to be absorbed from the network, which current is in phase with the voltage and brings PF close to 1 and reduces THD.
The PFCs generally comprise a converter provided with a power transistor and an inductor coupled to it and a control device coupled to the converter in such a way as to obtain from a network alternating input voltage a DC voltage regulated at the output. The control device is capable of determining the period of switched-on time Ton and the period of switched-off time Toff of the power transistor; the union of the period of Ton and the period of Toff time gives the cycle period or switching period of the power transistor.
The commercially available PFC circuit types are basically of two kinds that differ according to the different control technique used: pulse width modulation (PWM) control with fixed frequency wherein current is conducted continuously into an inductor of the power supply unit and variable frequency PWM control, also known as ‘transition mode’ (TM) because the inductor current is reset (i.e., zeroed) exactly at the end of each switching period. TM control can be operated both by controlling inductor current directly or by controlling the period of Ton time. The fixed-frequency control technique provides better performance but uses complex circuit structure whereas TM technique requires a more simple circuit structure. The first technique is generally used with high power levels whilst the second technique is used with medium—low power levels, normally below 200 W.
FIG. 1 is a diagrammatic view of a PFC pre-regulatory stage of the TM type comprising a boost converter 20 and a control device 1. The boost converter 20 comprises a full-wave diode rectifier bridge 2 with Vin network voltage input, a capacitor C1 (that is used as a high-frequency filter) with a terminal connected to the diode bridge 2 and the other terminal earthed, an inductor L connected to a terminal of the capacitor C1, an MOS power transistor M with the drain terminal connected to a terminal of the inductance L downstream of the latter and having the source terminal connected to a grounded resistance Rs, a diode D having the anode connected to the common terminal of the inductor L and the transistor M and the cathode connected to a capacitor Co, having the other terminal grounded. The boost converter 20 generates a DC output voltage Vout on the capacitor Co that is greater than the network maximum peak voltage, typically 400 V for systems powered by European network supplies or by a universal supply. Said output voltage Vout will be the input voltage of the DC-DC converter connected to the PFC.
The control device 1 has to maintain the output voltage Vout at a constant value by feedback control. The control device 1 comprises an error amplifier 3 suitable for comparing part of the output voltage Vout, in other words the voltage Vr deriving from Vr=R2*Vout/(R2+R1) (where resistances R1 and R2 are serially connected together and parallel to the capacitor Co) with a reference voltage Vref, for example 2.5V, and generates an error signal proportionate to their difference. The undulation frequency of output voltage Vout is twice that of the network voltage and is superimposed on the DC value. However, if the bandwidth of the error amplifier is significantly reduced (typically to below 20 Hz) by means of a suitable compensation network comprising at least one capacitor and we assume virtually stationary operation, in other words with constant direct effective input voltage and output load, said undulation will be greatly attenuated and the error signal will become substantially constant.
The error signal Se is sent to a multiplier 4, where it is multiplied by a signal Vi given by part of the network voltage rectified by the diode bridge 2. At the output of the multiplier 4 there is a signal Sm provided as a rectified sinusoidal current, the amplitude of which depends on the effective network voltage and on the error signal.
The signal Sm is sent to the inverting input of a PWM comparator 5 whereas the signal Srs across the resistance Rs is provided to the non-inverting input. If the signals Srs and Sm are the same, the comparator 5 sends a signal to a control block 6 that pilots the transistor M, which in this case switches it off. In this way the output signal Sm of the multiplier determines the peak current of the transistor M and this is then enveloped by a rectified sinusoidal current. A filter at the stage input eliminates the switching frequency component so that the current absorbed by the network has the form of the sinusoidal envelope.
After the MOS has been switched off the inductor releases the energy stored in it onto the load until it is completely emptied. At this point, the diode opens and the drain node of the MOS continues to float, so that its voltage moves towards the momentary input voltage through resonance oscillations between the stray capacitance of the node and the inductor inductance. The drain voltage is thus rapidly reduced, said drain voltage being coupled to the pin to which a block is connected that detects current 7 zeroes, which detector block belongs to the block 6, by means of the auxiliary coil of the inductor. The block 6 furthermore comprises an OR gate 8 having an input connected to the block 7 and the other input connected to a starter 10, suitable for sending a signal to the OR gate 8 at the instant of initial time; the output signal S of the OR gate 8 is the set input S of a set-reset flip-flop 11 having another input R, which is the output signal of the device 5, and having an output signal Q. The Q signal is sent to the input of a driver 12 that controls switch-up or switch-off of the M transistor.
A PFC absorbs an almost sinusoidal current that is not completely sinusoidal. There are two main sources of the residual distortion, which tends to maintain a not insignificant THD. The first is undulation with a frequency which is twice that of the network superimposed on the signal Se, if it is at a DC level present leaving the error amplifier, which introduces a 3rd harmonic distortion in the current reference generated by the multiplier. The second is cross distortion, which is seen as a short flat zone in the wave form of the network current IR, corresponding to the network voltage zeroes, which correspond to the minimum values VC1min of the voltage VC1 across the capacitor C1, as shown in FIG. 2, which shows the current IR and the voltage VC1 across the capacitor C1, in two cases with Vin=220Vac and input Pin power=80 W (FIG. 2a) and Vin=220Vac and Pin=40 W (FIG. 2b). The cross distortion increases as the PFC load decreases and as effective network voltage increases.
The cause of this distortion is the defective transfer of input-output energy that occurs near the zeroes of the network voltage. In this zone the energy stored in the inductor L is very low, insufficient to load the stray capacitance of the drain node of the MOS to the output voltage Vout (typically 400V) so as to enable the passage of current through the diode D and transfer the energy of the inductor L to output. As a result, the diode is not switched on for a certain number of switching cycles and the energy network remains confined in the resonating circuit consisting of said stray capacitance and of the inductor L. This phenomenon, which is accentuated by the presence of the high frequency filter capacitor C1 after the rectifier bridge, is shown in detail in FIG. 3, in which the current IR and the voltage Vdrain are shown in a zone in which the current IR is flat.